The present invention relates to memory circuits, and more particularly to memory circuits with row and column redundancy.
Despite advances in semiconductor process technology, integrated circuit memories may be manufactured with errors. Because a just single bit error may render a memory unusable, manufacturers have implemented various techniques to repair memories in which memory cells have been identified as faulty. For example, memories may include redundant rows or columns of memory cells. These redundant components are not used if the memory's non-redundant memory cells contain no manufacturing errors. If, however, a memory cell is faulty, a redundant memory component may be substituted for one of the non-redundant memory components such that the memory component including the faulty memory cell is no longer used. For example, a redundant row of memory cells is addressed in a row redundancy scheme only if a non-redundant row includes a faulty memory cell. Should a user desire to address the faulty row, the memory's row decoder addresses a substituted row instead.
It is conventional to organize memory rows into groups of one or more rows with regard to a row redundancy scheme. As used herein, each group of rows will be denoted as a “row-unit.” Should a memory cell be faulty in a row-unit, that row-unit is no longer used and a substitute row-unit is used instead. With regard to the row-units, it is conventional to organize memory row-units into blocks such that each block includes its own X decoder as well as a redundant row-unit. A similar group organization may be implemented for the columns. For example, FIG. 1 illustrates a memory including a plurality of 8 memory blocks arranged from a block 0 to a block 7. Each block includes a redundant row-unit and is addressed by a corresponding X decoder and a Y driver (for illustration clarity, only the X decoders are illustrated). Consider an arrangement in which each block includes sixty-four row-units. Each X decoder must then be able to identify whether a row-unit is bad. For example, a one-bit signal may be used as a flag indicating whether a row-unit in a given block is faulty. Should there be 64 row-units, a six-bit signal is sufficient to indicate the identity of the faulty row. Each X decoder may thus couple to a corresponding seven-bit-wide redundancy information bus to receive the flag and address signals (for illustration clarity, only X decoder 7 is shown coupled to its seven-bit-wide bus).
Although each X decoder may thus identify whether a faulty row-unit exists, the X decoder must include a decoding portion to decode the contents of the bus, thereby occupying valuable die space. Moreover, the routing of the necessary buses complicates design. Finally, the demand on the input/output (I/O) resources can be considerable. For example, 56 I/O pins would need to be reserved for the row redundancy information for the memory of FIG. 1 (7 bits times 8 blocks).
Accordingly, there is a need in the art for improved row and column redundancy architectures.